1. Field of the Invention
This invention relates to circuits coupled to an integrated circuit that provides protection from electrostatic discharge (ESD) events. More particularly, this invention relates to circuits that will prevent a differential voltage level between two different power supply voltage terminals from exceeding a specified voltage level and thus prevent damage to the integrated circuit.
2. Description of Related Art
Integrated circuits often have either multiple terminals connected to a single power supply voltage source or multiple isolated power supply voltage sources. The power supply voltage sources are connected through separate distribution networks to the internal integrated circuits. The structure of the internal integrated circuits may have a core logic section and a peripheral logic section. In order to isolate noise, such as caused by simultaneous switching of driver circuits in the peripheral logic section or impedance mismatch on transmission line connected to an input/output (I/O) pad, the peripheral logic section would have a separate power supply distribution network from that of the core logic section. Similarly, the internal circuits may include analog circuits requiring multiple power supply voltage sources and need to be isolated from the core logic and peripheral logic section to prevent conduction of noise to the analog circuits.
While the core logic section and the peripheral logic section often have a common power supply voltage source, it is not uncommon for the core logic section to have a power supply voltage source of a different voltage level than the peripheral logic section. For instance, the peripheral logic section may have a power supply voltage source of 5.0V and the core logic section may have a power supply voltage source of 3.3V. It is further common that the analog section require even different voltage levels than the core logic section or the peripheral logic section. Further, the internal integrated circuits may have implementations with multiple core logic sections, multiple peripheral logic sections, and multiple analog core sections. Each section will have a separate voltage distribution network for the power source and return paths.
An ESD event is commonly a pulse of a very high voltage typically of several kilovolts with a moderate current of a few amperes for a short period, typically about 100 nanoseconds. The common source of an ESD event is bringing the integrated circuit in contact with a human body or a machine such as an integrated circuit tester and handler.
If an I/O pad is contacted and subjected to an ESD event, the power supply distribution network of the peripheral logic section connected to the I/O pad begins to change relative to the voltage level of the power supply voltage source connected to the core logic section. This change can cause damage in subcircuits that form an interface between the core logic section and the peripheral logic section. FIG. 1 illustrates a structure of the prior art of a voltage clamping circuit employed to prevent damage between the distribution networks of two separate power supply voltage sources. The structure of FIG. 1 illustrates a two-staged voltage clamping circuit, which may be expanded by the addition of more stages.
A substrate has the distribution networks 55 and 60 to connect the separate power supplies Vsup1 and Vsup2 to the internal circuitry 65. To provide the protection from any ESD events, the voltage clamping circuit is connected between the distribution networks 55 and 60 to connect the separate power supplies Vsup1 and Vsup2. The voltage clamping circuit has an N-type impurity diffused to a lightly doped level into the P-type substrate to form the N-wells 10 and 15. The N-type impurity is diffused to a high concentration level into the N-wells 10 and 15 to form the heavily doped N-regions 20, 25, 35, and 45. A P-type material is diffused to a high concentration into the N-wells 10 and 15 to form the heavily doped P-regions 30 and 40. Simultaneously the P-type material is diffused into the substrate 5 to form the P-region 50. Contact metallurgy is alloyed to the P-type region 50 to form a contact that is connected to the ground reference distribution system 75.
Contact metallurgy is alloyed to the P-type regions 30 and 40 to form contacts that are respectively connected to the distribution networks 55 and 60 for the power supply voltage sources Vsup1 and Vsup2. Contact metallurgy is alloyed to the N-type regions 20 and 25 and to the P-type region 40 to form a contact that serially interconnects the two stages of the voltage clamping circuit. Contact metallurgy is alloyed to the N-type regions 35 and 45 to form contacts that are connected to the distribution network 60 that is connected to the power supply voltage source Vsup2.
The diode D1 70a is formed at the junction of the P-region 30 and N-well 10 in conjunction with the N-region 20. Similarly, the diodes D270b, D3 70c, and D470d are formed at the junction of the P-regions 30 and 40 and N-wells 10 and 15 in conjunction respectively with the N-regions 25, 35, and 45. Further the emitter of the vertical PNP transistor 75a is formed by the P-region 30, the base being the N-well 10, and the collector being the P-type substrate 5. Likewise, the emitter of the vertical PNP transistor 75b is formed by the P-region 40, the base being the N-well 15, and the collector being the P-type substrate 5.
Referring now to FIG. 2 for a discussion of the operation of the voltage clamping circuit of the prior art. In this example, the voltage clamping circuit has multiple PNP transistors 75a, 75b, . . . , 75m, . . . , 75n serially connected emitter to base. The emitter of first PNP transistor 75a is connected to the distribution network 55 of the power supply voltage source Vsup1. The base of the last PNP transistor 75n is connected to the distribution network 60 of the power supply voltage source Vsup2. The collectors of the PNP transistors 75a, 75b, . . . , 75m, . . . , 75n are connected to the ground reference distribution system 75. If the voltage level present on the distribution network of the power supply voltage supply Vsup1 increases to a threshold level greater than the voltage level of the power supply voltage source Vsup2, the base-emitter diodes of the PNP transistors 75a, 75b, . . . 75m, . . . , 75n begin to conduct to clamp any voltage difference between the power supply voltage source Vsup1 and the power supply voltage source Vsup2 to maintain the threshold level difference between the power supply voltage sources Vsup1 and Vsup2.
The threshold level is determined by the number of serially connected PNP transistors 75a, 75b, . . . , 75m, . . . , 75n and is calculated from the formula:
Vt=mVdxe2x88x92Vom*m(mxe2x88x921)*ln(xcex2+1)/2
where:
Vt is threshold level of the voltage clamping circuit.
m is the number of PNP transistors 75a, 75b, . . . , 75m, . . . , 75n. 
Vd voltage developed across each individual base emitter junction of the PNP transistors 75a, 75b, 75m, . . . , 75n. 
Vo is determined by the formula:       V    o    =      KT    q  
xe2x80x83where:
K is Boltzman""s constant.
T is the temperature.
q is electrical charge of an electron.
It is known that the main cause in a decrease in the breakdown or conduction voltage of during an ESD event is the leakage current from of the base-emitter junction of the PNP transistors 75a, 75b, . . . , 75m, . . . , 75n. Thus, as the number of PNP transistors 75a, 75b, . . . , 75m, . . . , 75n increases, the threshold level does not increase concomitantly.
Other ESD device structures as illustrated in U.S. Pat. No. 5,674,761 (Chang, et al.), U.S. Pat. No. 5,856,214 (Yu), and U.S. Pat. No. 6,096,584 (Ellis-Monaghan, et al.) provide ESD devices structures that prevent damage to internal circuitry by preventing excess voltage as applied to input/output pads from damaging internal circuitry.
Polycrystalline silicon diodes are well known in the art as illustrated by U.S. Pat. No. 4,616,404 (Wang, et al.). Wang, et al. describes a method of making improved lateral polycrystalline silicon diode by treating plasma-etched sidewalls to remove defects. The lateral polycrystalline diode is characterized by low reverse current leakage, a breakdown voltage of at least five volts, and low series resistance permitting high current flow before being limited by saturation. The polycrystalline silicon diode has a polycrystalline silicon block formed on a substrate. The polycrystalline silicon block has a first zone sufficiently doped to provide a first semiconductor type and a second zone sufficiently doped to provide a second semiconductor type. The junction where the two zones are adjoined form a diode.
Another polycrystalline diode is described in U.S. Pat. No. 6,229,157 (Sandhu). The polycrystalline silicon diode of Sandhu has a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polycrystalline silicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polycrystalline silicon material. An insulative material is deposited in the seam. The polycrystalline silicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.
A polycrystalline diode structure that has a high voltage tolerance, which is to be used for mixed-voltage, and mixed signal and analog/digital applications is described in U.S. Pat. No. 6,232,163 and U.S. Pat. No. 6,015,993 (both to Voldman, et al.). The diode includes a polycrystalline silicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. A block mask is formed over the gate structure when defining the depleted-polycrystalline silicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film.
An application of polycrystalline silicon diodes is shown in xe2x80x9cOn-Chip ESD Protection Design by Using Polysilicon Diodes in CMOS Process,xe2x80x9d Ker et al., IEEE Journal Of Solid-State Circuits, IEEE, New York, N.Y., VOL. 36, NO. 4, April 2001, pp. 676-686 and xe2x80x9cOn-Chip ESD Protection Design for GHz RF Integrated Circuits by Using Polycrystalline silicon Diodes in sub-quarter-micron CMOS Process,xe2x80x9d Chang and Ker, Proceedings 2000 Electrical Overstress and Electrostatic Discharge Symposium, IEEE, New York, N.Y., 2000, pp. 3A 4.1-3A 4.10. These papers describe applications using polycrystalline silicon diodes as the ESD clamp devices in CMOS process. Different process factors are experimentally evaluated to find the suitable doping concentration for optimizing the polycrystalline silicon diodes for both on-chip ESD protection design and the application requirements of the smart-card IC""s.
Another application for polycrystalline silicon diodes for ESD applications is described in xe2x80x9cDesign of the Turn-On Efficient Power-Rail ESD Clamp Circuit with Stacked Polysilicon Diodes,xe2x80x9d Ker and Chen, Proceeding of the 2001 International Symposium on Circuits and Systems, IEEE, New York, 2001, pp. IV-758-IV-761. Ker and Chen detail a novel power-rail ESD clamp circuit design by using stacked polycrystalline silicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. The power-rail ESD clamp circuit employing the polycrystalline silicon diodes as described in Ker and Chen achieves a human body model ESD level has been successfully improved from the originalxcx9c200V to become 3 Kv.
An object of this invention is to provide an ESD protection circuit that will protect integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources.
Another object of this invention is to provide an ESD protection circuit having a lateral diode constructed of polycrystalline silicon characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.
To accomplish at least one of these objects as well as other objects, an electrostatic discharge circuit that includes a plurality of serially connected polycrystalline silicon diodes formed on a surface of a substrate is connected between a first power supply voltage source and a second power supply voltage source to protect internal integrated circuits from damage due to an electrostatic discharge. Each diode of the plurality of serially connected polycrystalline diodes has a first electrode and a second electrode. The plurality of serially connected polycrystalline diodes has a first diode, which has its first electrode connected to the first power supply voltage source, and a last diode, which has its second electrode connected to the second power supply voltage source.
The first electrode of each diode of the plurality of serially connected polycrystalline silicon diodes is a first region of polycrystalline silicon being heavily doped with an impurity of a first type. Further, the second electrode of each diode of the plurality of serially connected polycrystalline diodes is a second region of polycrystalline silicon being heavily doped with an impurity of a second type. The second region being adjoined to the first region to form an electrical junction. Each diode is formed on a shallow trench isolation formed within the substrate. During formation of each diode a resistor protection oxide formed as an overlay to protect a portion of the first and second regions at the junction.
Generally, the first electrode of each polycrystalline silicon diode is defined as cathode and the second electrode of each polycrystalline silicon diode is defined as an anode. To maintain this definition, the impurity of the first type is an N-type impurity having a density of from approximately 1015 atoms/cmxe2x88x923 to approximately 1021 atoms/cmxe2x88x923. The impurity of the second type is a P-type impurity having a density of from approximately 1015 atoms/cm xe2x88x923 to approximately 1021 atoms/cmxe2x88x923.
The width of each of the diodes and the thickness of the polycrystalline silicon diodes and the doping levels of the first and second electrodes of each diode determines the resistivity of the diode and thus the current capacity of the diodes. The preferred thickness of the polycrystalline silicon diodes is preferably from approximately 1000 xc3x85 to approximately 3000 xc3x85. The width of polycrystalline silicon diodes is preferably from approximately 0.5 xcexcm to approximately 100 xcexcm.
The number of the plurality of serially connected polycrystalline silicon diodes of the electrostatic discharge circuit is determined by the formula:   n  ≥                    V        noise            +              "LeftBracketingBar"                  Vx1          -          Vx2                "RightBracketingBar"                    V      T      
where:
n is the number serially connected of polycrystalline silicon diodes,
Vnoise is the maximum voltage level difference allowed to be present on the internal integrated circuits between the first power supply voltage source and the second power supply voltage source,
Vx1 is the magnitude of the first power supply voltage source,
Vx2 is the magnitude of the second power supply voltage source, and
VT is the threshold voltage of each polycrystalline silicon diodes.